1. Field of the Invention
This invention relates generally to dynamic semiconductor memory devices, and more particularly, it relates to an improvement in correction of reading errors in a memory cell array structure of a twisted bit line system.
2. Description of the Background Art
FIG. 13 is a block diagram showing a structure of a conventional semiconductor memory device. FIG. 13 shows an example of a 64 k bit memory device having eight inputs A0 to A7 as address inputs.
Referring to FIG. 13, the memory cell array 1 comprises a plurality of memory cells arranged in a plurality of rows and columns. A plurality of word lines are provided corresponding to the plural rows of the memory cell array 1 and a plurality of bit lines are provided corresponding to the plural columns of the same.
An RAS buffer 4 activates a row address buffer 5, a .phi.p generation circuit 6, a .phi.x generation circuit 7 and a sense amplifier control circuit 8 in response to an externally applied row address strobe signal RAS. The .phi.p generation circuit 6 and the .phi.x generation circuit 7 generate a precharge signal .phi.p and a driving signal .phi.x at prescribed timings, respectively. The row address buffer 5 latches externally applied address signals A0 to A7 and applies a part of the signals as row address signals RA2 to RA7 to the row predecoder 9 and applies the remainder signals as row address signals RA0 to RA1 to the .phi.x subdecoder 10. The row predecoder 9 predecodes row address signals RA2 to RA7 applied from the row address buffer 5 and applies row selection signals Xi, Xj and Xk to the row decoder group 11. The row decoder group 11 selects four rows in the memory cell array 1 based on the row selection signals Xi, Xj and Xk. The .phi.x subdecoder 10 applies subdecode signals .phi.xl to .phi.x4 to the word driver group 13 and the dummy word signal generation circuit 12 based on the row address signals RA0 to RA1 applied from the row address buffer 5, in response to the driving signal .phi.x from the .phi.x generation circuit 7.
The word driver group 13 drives word lines for one row out of the four rows selected by the row decoder group 11 in response to the subdecode signals .phi.x1 to .phi.x4. Information in the memory cells connected to the driven word lines is read out on each bit line. On this occasion, either a dummy word line DWLo or a dummy word line DWLe is driven to fall by the dummy word line signal generation circuit 12 dependent on the bit line BL or BL to which the memory cells selected by the driven word lines are connected. The sense amplifier control circuit 8 operates the sense amplifier group 14 at a prescribed timing. The sense amplifier group 14 amplifies the information on each bit line.
Meanwhile, the CAS buffer 15 activates a column address buffer 16 and a read/write buffer 17 in response to an externally applied column address strobe signal CAS. The column address buffer 16 latches externally applied address signals A0 to A7 and applies the same to the column predecoder 18 as the column address signals. The column predecoder 18 predecodes the column address signals and applies column selection signals to the column decoder group 19. The column decoder group 19 selects one column in the memory cell array 1 based on the column selection signal. In this manner, one word line and one bit line are selected and reading or writing of information is carried out for the memory cell at the intersection. In FIG. 13, only the selected one word line WL, and, the selected one bit line BL and a memory cell MC at the intersection thereof are shown.
Reading or writing of information is selected by the read/write buffer 17. The read/write buffer 17 activates an input buffer 21 or an output buffer 22 in response to an externally applied read/write signal R/W. When the input buffer 21 is activated, the input data D.sub.in is written in the memory cell MC which is selected as described above. When the output buffer 22 is activated, the information stored in the memory cell MC which is selected as described above is read as the output data D.sub.out. Each of the above described circuits is formed on the same semiconductor chip 23.
FIG. 14 shows a structure of one portion of the row predecoder 9 shown in FIG. 13, illustrating the circuit portion for generating the row selection signal Xi, which is any one of the signals X1, X2, X3 and X4.
A gate circuit 91 receives the row address signal RA2 and outputs the same signal RA2 and the inverted signal RA2 thereof. A gate circuit 92 receives the row address signal RA3 and outputs the same signal RA3 and the inverted signal RA3 thereof. Either the signal RA2 or RA2 and either the signal RA3 or RA3 are inputted to the gate circuits 93, 94, 95 and 96. The combinations of the signals RA2 or RA2 and RA3 or RA3 inputted to the gate circuits 93 to 96 are different from each other. Row selection signals X1 to X4 are outputted from the gate circuits 93 to 96, respectively. One of the row selection signals X1 to X4 rises to high (H) level and the other signals remain low (L) level in response to the levels of the row address signals RA2 and RA3.
The row selection signal Xj in FIG. 13 means one of the signals X5, X6, X7 and X8, while Xk means one of the signals X9, X10, X11 and X12. The row selection signals X5 to X8 are generated in the same manner as in FIG. 14 by the row address signals RA4 and RA5, while the row selection signals X9 to X12 are generated in the same manner as in FIG. 14 by the row address signals RA6 and RA7.
FIG. 15 shows the structure of .phi.x subdecoder 10 in FIG. 13. The .phi.xl generation circuit 101, .phi.x2 generation circuit 102, .phi.x3 generation circuit 103 and .phi.x4 generation circuit 104 respectively receive the row address signal RA0 or the inversion signal RA0 thereof and the row address signal RA1 or the inversion signal RA1 thereof, and output subdecode signals .phi.xl, .phi.x2, .phi.x3 and .phi.x4, respectively, in response to the driving signal .phi.x. One of the subdecode signals .phi.xl, .phi.x2, .phi.x3 and .phi.x4 rises to H level and the other remain L level in response to the levels of the row address signals RA0, RA1 and of the inversion signals RA0, RA1 thereof.
FIG. 16 shows a detailed structure of the memory cell array 1 and the peripheral portion thereof in FIG. 13.
The memory cell array 1 includes 4 m word lines WL and a plurality of bit line pairs BL and BL which are arranged intersecting with each other in the array 1, where m is a positive integer. Two dummy word lines of DWLo and DWLe are arranged on a side of those word lines WL (WL1 to WL4). A memory cell MC is provided at an intersection of each word line WL and the bit line BL or BL, while dummy cells DCo and DCe are provided at intersections of the dummy word line DWLo and the bit line BL, and DWL and BL, respectively. 4 m word drivers 13a are provided corresponding to the 4 m word lines WL (WL1 to WL4). The word lines WL (WL1 to WL4) are connected to the corresponding word drivers 13a. 4 m word lines WL and 4 m word drivers 13a are divided into m sets, each comprising four word lines WL and four word drivers 13a. m row decoders 11a are provided corresponding to the m sets. Each row decoder 11a selects four word drivers 13a of the corresponding set.
A plurality of sense amplifiers 14a and a plurality of column decoders 19a are provided corresponding to the plurality of bit line pairs BL and BL. Each bit line pair BL and BL is connected to the corresponding sense amplifier 14a and the corresponding column decoder 19a.
Now, the operation of the circuit shown in FIG. 16 will be described.
One of the row decoders 11a is selected based on the row selection signals Xi, Xj and Xk. The selected row decoder 11a activates four word drivers 13a of the corresponding set. One of the four word drivers 13a activates the corresponding word line WL in response to the subdecode signals .phi.xl to .phi.x4. Consequently, the information in the memory cell MC connected to the word line WL is read onto each bit line BL or BL and is amplified by the sense amplifier 14a. On this occasion, if the selected memory cell is connected to the bit line BL, the dummy word line DWLo falls. Then, one of the column decoders 19a is selected in response to the column address signal. In writing, the information is written onto the bit line pair BL and BL connected to the selected column decoder 19a. In reading, the information on the bit line pair BL and BL connected to the selected column decoder 19a is read.
FIG. 17 shows a particular circuit structure of the row decoder 11a and the word driver 13a shown in FIG. 15.
The row decoder 11a comprises N channel MOS transistors Q1 to Q4, and P channel MOS transistors Q5 to Q7. The transistors Q5 and Q6 are coupled between the supply potential Vcc and a node N1. A precharge signal .phi.p is applied to the gate of the transistor Q5 and the gate of the transistor Q6 is connected to a node N2. The transistors Q1, Q2 and Q3 are coupled in series between the node N1 and the ground potential. Row selection signals Xi, Xj and Xk are applied to the gates of the transistors Q1, Q2 and Q3, respectively. As described above, Xi denotes one of X1 to X4, Xj denotes one of X5 to X8, and Xk denotes one of X9 to X12. The combination of the row selection signals Xi, Xj and Xk applied to each row decoder 11a differs from that of other row decoders 11a. The transistor Q7 is coupled between the supply potential Vcc and the node N2, and its gate is connected to the node N1. The transistor Q4 is coupled between the node N2 and the ground potential, and its gate is connected to the node N1. The transistors Q4 and Q7 constitute an inverter. Therefore, the level of the node N2 and the level of the node N1 are opposite to each other.
The nodes N1 and N2 of each row decoder 11a are connected to the four word driver 13a of the corresponding set. Each word driver 13a comprises N channel MOS transistors Q8, Q9 and Q10. The transistor Q9 is coupled between one of the subdecode signals .phi.xl to .phi.x4 and a word line WL, and its gate is connected to the node N2 of the corresponding row decoder 11a through the transistor Q8. The transistor Q10 is coupled between the word line WL and the ground potential, and its gate is connected to the node N1 of the corresponding row decoder 11a. The gate of the transistor Q8 is coupled to the supply potential Vcc. The word driver 13a in each set are coupled to respective different ones of the subdecode signals .phi.xl, .phi.x2, .phi.x3 and .phi.x4.
Next, the operation of the row decoder 11a and the word driver 13a will be described. When the precharge signal .phi.p is at L level, the transistor Q5 is in the on state and the potential of the node N1 is at H level (Vcc level). Therefore, the transistor Q10 of the word driver 13a is in the on state and the potential of the word line WL is at L level (ground level). When the precharge signal .phi.p rises to H level, the transistor Q5 turns off. When the row selection signals Xi, Xj and Xk applied to the gates of the transistors Q1, Q2 and Q3 all rise to H level, the transistors Q1, Q2 and Q3 all turn on, so that the potential of the node N1 falls to L level and the potential of the node N2 rises to H level. Consequently, the transistor Q10 of the word driver 13a turns off. When one of the subdecode signals .phi.xl to .phi.x4 rises to H level, the potential of the corresponding one of the word line WL1 to WL4 rises to H level.
The level of the dummy word line DWLo falls at the rise of either the word line WL1 or WL3 and the level of the dummy word line DWLe falls at the rise of either the word line WL2 or WL4 under the control of the dummy word signal generating circuit 12. A circuit for realizing such operation is shown in FIG. 18. Referring to FIG. 18, the dummy word line DWLo is provided as the output of the two-input NOR of the subdecode signals .phi.xl and .phi.x3, and the dummy word line DWLe is provided as the output of the two-input NOR of the subdecode signals .phi.x2 and .phi.x4.
FIG. 19 shows a detailed structure of the memory cell array and the sense amplifier shown in FIG. 13.
Referring to FIG. 19, word lines WL1, WL2 and dummy word lines DWLo, DWLe are arranged in the direction intersecting with the bit lines BL and BL. A memory cell selection transistor QM and a capacitor C are connected in series as a memory cell at an intersection of the word line WL1 and the bit line BL. Similarly, a memory cell is connected at an intersection of the word line WL2 and the bit line BL. A dummy cell selection transistor QD and a dummy capacitor DC0 are connected in series as a dummy cell at an intersection of the dummy word line DWLo and the bit line BL. Similarly, a dummy cell is connected at an intersection of the dummy word line DWLe and the bit line BL. Respective one ends of the bit lines BL and BL are connected to a precharge potential V.sub.PRC through precharge transistors QP and QP'. The precharge potential V.sub.PRC is maintained at a potential Vcc/2. The bit lines BL and BL are connected to each other through a transistor QE. A precharge signal .phi..sub.PRC is applied to the respective gates of the transistors QP, QP' and QE. The bit lines BL and BL are connected with a sense amplifier SA for detecting and amplifying a potential difference appearing on the bit lines. The ground potential is applied to the sense amplifier SA through the transistor Q1 and the supply potential Vcc is applied thereto through the transistor Q2. A sense amplifier activation signal .phi.s is applied to the gate of the transistor Q1. A sense amplifier activation signal .phi.s is applied to the gate of the transistor Q2. The respective other ends of the bit lines BL and BL are connected to an input/output line I/O through a transistor QT and to an input/output line I/O through a transistor QT'. An output signal from a column decoder is applied to the gates of the transistors QT and QT'.
In the following, the operation of the semiconductor memory device shown in FIGS. 13 to 19 will be described with reference to the timing chart of FIG. 20.
In a standby period of the precharge signal .phi.p at L level, the potential of the node N1 of each row decoder 11a in FIG. 17 is at H level and those of the node N2 thereof is at L level. Consequently, the potentials of all the word lines WL are at L level. The dummy word lines DWLo and WLe are both at H level in response to the subdecode signals .phi.xl to .phi.x4 all at L level. After the precharge signal .phi.p rises to H level, the signals Xi, Xj and Xk applied to the selected row decoder 11a are all raised to H level. As a result, the potential of the node N1 falls to L level and the potential of the node N2 rises to H level. Thus, the corresponding four word drivers 13a are selected. Then, when one of the subdecode signals .phi.xl to .phi.x4 rises to H level, the potential of the corresponding word line WL is raised to H level by the word driver 13a. At the same time, either the dummy word line DWLo or DWLe falls by the logic shown in FIG. 18.
On the other hand, the precharge signal .phi..sub.PRC falls to L level before the potential of the corresponding word line rises, and the bit line is in the floating state. For example, if the word line WL1 is selected, the potential of the word line WL1 rises to H level and the dummy word line DWLo is selected at the same time and falls to L level. Accordingly, the memory cell selection transistor QM is turned on and the memory cell MC is connected to the bit lines. For example, if the potential of H level is stored in the memory cell MC connected to the bit line BL, the potential of the bit line rises by a value determined by its stray capacitance C.sub.BL and the capacitance Cs of the memory cell MC. Meanwhile, the potential of the bit line BL is maintained at Vcc/2 and it serves as a reference potential for the potential of the bit line BL. Subsequently, when the sense amplifier activation signal .phi.s rise to H level and the sense amplifier activation signal .phi.s falls to L level to activate the sense amplifier SA, the potential of the bit line BL becomes Vcc and the potential of the bit line BL becomes the ground potential, whereby the sense operation is completed.
In the above described sequential operation, the potential of the bit line BL rises due to a capacitance coupling through a stray capacitance Cp existing between the connection portion of the bit line BL of the memory cell selection transistor QM shown in FIG. 21 and the word line WL1 at the rise of the word line WL1, thereby affecting a permissible operation range of a read signal. Particularly, if the potential of L level is stored in the memory cell MC, the potential of the bit line BL rises due to the capacitance coupling to a higher level than the initially expected level which should be lower than the potential of the bit line BL, causing L level information to be read as H level information. A dummy cell DC is provided to offset such potential change of the bit line BL. By lowering the potential of the dummy word line DWLo, it is possible to apply, to the bit line BL, a potential change of an equal amount opposite to that caused in the bit line BL at the rise of the word line WL1. More specifically, influence on the operation of reading the potential change is to be offset by applying the potential change of the equal amount in the opposite direction to the bit line BL.
However, due to noises between the adjacent bit line pairs, caused by the capacitance between the bit lines, the amplitude of the voltage for reading is lowered and the above described method is still unsatisfactory as the measures for preventing errors in reading of data. This will be explained in more detail in the following.
Referring to FIG. 22, it is assumed that each bit line has a capacitance C1 with respect to the ground potential (fixed potential) through the corresponding cell plate or substrate, a capacitance C2 with respect to the bit line to be paired, and a capacitance C3 with respect to the bit line of the adjacent bit line pair. The length of each bit line is l and the memory cell capacity is Cs.
It is also assumed that each memory cell stores charge of H level: Cs Vcc (for writing of Vcc) and charge of L level: 0 (for writing of OV).
If the precharge level of each bit line is Vcc/2, a memory cell connected to a bit line BL1 for example is selected and if a dummy cell is connected to the bit line BL1, the potentials V.sub.BL1 and V.sub.BL1 of the bit lines BL1 and BL1 are as follows: ##EQU1## where .DELTA.V.sub.BL0, .DELTA.V.sub.BL1, .DELTA.V.sub.BL1 , and .DELTA.V.sub.BL2 are potential changes in the bit lines indicated by the letters, respectively.
From the above indicated equations (1) to (3), considering that the bit lines BL1 and BL1 have the equal precharge level, the voltage difference between the bit line pairs is obtained in the following manner, by calculations of (1)-(3) and (2) -(3). ##EQU2## "+", which is attached to the numerical formula "1/(1+.alpha.).multidot..beta./2", indicates reading of H level and "-", which is attached to the numerical formula "1/(1+.alpha.).multidot..beta./2", indicates reading of L level.
The first term of the right side of the equation (4) represents an inherent voltage difference for reading and the second term thereof represents a noise component through a coupling capacitance from the bit lines BL0 and BL2 of the adjacent bit line pairs.
If a bit line pitch is decreased as a result of enhancement of the integration scale of the memory, the capacitance C3 between the bit line pairs increases and the value of the second term of the equation (4) becomes large. Accordingly, the voltage for reading is adversely affected and the permissive range for reading is reduced, resulting in the deterioration of the soft error ratio and causing erroneous operation.
Under the circumstances, in order to solve the problems of the above described device, the inventors of the present invention proposed "Bit Line Structure for Semiconductor Memory Device" of U.S. application Ser. No. 131,633, which discloses a semiconductor memory device capable of completely suppressing lowering of the amplitude of the reading voltage due to the noise between the adjacent bit line pairs by the capacitance between the bit lines.
In the above mentioned semiconductor memory device, intersections are provided at one or more portions on the bit line pairs so that the capacitance coupling noise applied to the respective bit lines of the pair from the adjacent bit line pairs can be made completely equal, thereby preventing lowering of the voltage difference for reading.
In the following, the above described improved semiconductor memory device will be described with reference to FIG. 23.
In this improvement example, as shown, the bit line pairs (BL0, BL0, BL1, BL1 etc.) are divided in four equal sections and those bit lines are twisted at the equally divided points CP1, CP2 and CP3 in the following manner.
(1) The bit lines BL0 and BL0 are twisted at CP2. PA1 (2) The bit lines BL1 and are twisted at CP1 and CP3. PA1 (1)' The bit lines BL2 and BL2 are twisted at CP2. PA1 (2)' The bit lines BL3 and BL3 are twisted at CP1 and CP3. PA1 (1) The capacitance coupling noises .DELTA.V.sub.BLl , and .DELTA.V.sub.BL1, applied to the bit line pairs BL1 and BL1 from the respective adjacent bit line pairs are as follows: ##EQU3## where .DELTA.V.sub.BL0 is the component associated with section "a" of FIG. 23, .DELTA.V.sub.BL2 is the component associated with section "b", etc. and accordingly the two noises are completely equal.
More specifically, the odd-numbered bit line pairs starting from the bit line pairs BL0 and BL0 are twisted at CP2 and the even-numbered bit line pairs are twisted at CP1 and CP3. In consequence, the capacitance coupling noise applied to the respective bit line pairs from the adjacent bit line pairs is expressed as below, as in the previously described conventional example.
(2) The capacitance coupling noises .DELTA.V.sub.BL2, and .DELTA.V.sub.BL2, applied to the bit lines BL2 and BL2 from the respective adjacent bit line pairs are as follows: ##EQU4## thus, the two noises are completely equal.
Similarly the capacitance coupling noises applied to the respective bit lines of all the pairs from the adjacent bit line pairs are entirely equal.
(3) Also regarding the bit line pair BL0 and BL0 at the end of the memory cell array, the capacitance coupling noises applied thereto are as indicated below: ##EQU5## and thus the two noises are entirely equal.
Thus, in this improvement example, the capacitance coupling noises applied to the respective bit lines from the adjacent bit line pairs at the time of reading signals are entirely equal, which makes it possible to completely prevent reduction of the voltage difference in reading due to such noises and to enlarge the permissible range for reading and to improve the soft error ratio.
Next, the disadvantages of this improvement example will be described. Let us assume a case, in which a dummy cell system is applied to the bit line pairs which intersect at specified points as in the above indicated improvement example. FIG. 24 shows an arrangement estimated in the case of applying the conventional dummy cell system in FIG. 19. In FIG. 24, only the word lines WL1 and WL2 are shown typically for each block. The mark o at the intersection of each word line and each bit line indicates that a memory cell is provided. The mark at the intersection of a dummy word line and its bit line indicates that a dummy cell is provided.
As for the dummy cell, it is necessary to select the one connected to the same bit line as for the memory cell and in the case of FIG. 24, the selection is effected in the following manner.
(1) DWLo is selected if a word line, e.g., WL1 is selected from the block d, and DWLe is selected if the word line WL2 for example is selected.
(2) If the word lines WL1 and WL2 from the block c are selected, half of the total number of the bit line pairs are always found to be unacceptable (BL1, BL1, BL3, BL3 in FIG. 24) even if either DWLo or DWLe is selected.
Also for the blocks b and a, half of the total number of the bit line pairs are found to be unacceptable.
Therefore, the conventional dummy cell system cannot be applied to the cases including intersections of the bit line pairs.
FIG. 25 is a plan view showing intersection parts of the conventional bit lines and FIG. 26 is a sectional view taken along XXVI--XXVI in FIG. 25.
Referring to those figures, an isolation oxide film 58 defining an active region is formed on a main surface of a semiconductor substrate 55. Impurity regions 59a and 59b defining transistor and capacitor regions of a memory cell are formed in the active region. A cell plate defining a capacitor is formed through an insulating film over the impurity region 59b. An interlayer insulating film 60 is formed to cover the whole main surface of the semiconductor substrate 55. Word lines 51 for controlling conduction of the memory transistor of the memory cell are formed in the interlayer insulating film 60. Bit lines 52 are formed on the interlayer insulating film 60 in the direction perpendicular to the word lines 51. Each bit line 52 is connected to the corresponding impurity region 59a through a contact hole 53 formed in the interlayer insulating film 60. Each bit line 52 is formed of an aluminum connection or the like. In a bit line under a twisted portion of the bit line pair, the aluminum connection is connected through a contact 56 through a polysilicon connection layer 54. The twisted portions of the conventional bit lines are formed as described above and if the areas occupied by the intersection parts become large although such intersection parts are necessary, such large areas are disadvantageous in enhancement of the integration scale of the device.